SDRAM Timing questions upgrading iMac TFT 15 - 800Mhz

Eneko, Welcome to the discussion area!

If Crucial recommends that memory for your iMac it will work or they will replace it with memory that will.

It doesn't matter if the current module is CL2 or CL3. The 2 don't have to be matched in any way.

The system bus speed of your machine is 100 MHz. Most PC133 RAM on the market is CL=3 at 133 MHz and CL=2 at 100 MHz. My guess is that it will run at CL=2. Even if it isn't, the memory controller should be able to handle it just fine at CL=3.

I don't know how Apple handles it, but some memory systems are know to default to the slowest latency setting for all memory to be on the safe side. This way, all memory locations can be treated the same. Others will control each module separately depending on its fastest speed, although this is more complex.

Apple Hardware Test can give more detailed info. You'll probably see multiple timings. It'll look something like CL=3(7.5), CL=2(10.0). The numbers stand for 7.5 nanoseconds (133 MHz) and 10.0 nanoseconds (100 MHz).

http://www.everymac.com/systems/apple/imac/stats/imac800fp.html

Just to be clear... CL (CAS Latency) is not directly tied to PC100, PC133, or any other clock speed.

Duane:

i Just to be clear... CL (CAS Latency) is not directly tied to PC100, PC133, or any other clock speed.

It can be if the memory controller can take advantage of it. It's just a representation of the number of clock periods it takes from the time the READ command and column address (CAS stands for "column address strobe") are sampled, and the first data is available. The absolute latency (delay) of the memory inside the chip is independent of the clock frequency (i.e. the system bus clock) fed to the synchronous interface. A faster clock can mean you need to use a higher value for CL.

It happens that for a -75 (min 7.5 ns clock period or max 133 MHz freq) part, CL can be safely set to 3 at 133 MHz or 2 at 100 MHz.

SPEED GRADE/CLOCK FREQUENCY/ACCESS TIME/SETUP TIME/HOLD TIME
-75 / 133 MHz / 5.4ns (CL=3) / 1.5ns / 0.8ns
-75 / 100 MHz / 6ns (CL=2) / 1.5ns / 0.8ns

http://download.micron.com/pdf/datasheets/dram/sdram/512MbSDRAM.pdf

A faster clock can mean you need to use a higher value for CL.

Again CL and RAM clock speed are not directly related. You will find PC2700 (which runs at 333 MHz) and PC3200 (which runs at 400 MHz) RAM with CL's of 2 or 3.

Duane:

i Again CL and RAM clock speed are not directly related. You will find PC2700 (which runs at 333 MHz) and PC3200 (which runs at 400 MHz) RAM with CL's of 2 or 3.

PC2700 does not run at 333 MHz. It runs at 166 MHz with data transferred on both clock edges. PC3200 runs at 200 MHz. Also - the rating you see is related to maximum clock frequency and not recommended operation at a slower clock frequency. Some modules can be run at a lower CL with a lower clock frequency.

Did you read the Micron specs I linked? For a typical -75 speed rated single-data rate SDRAM part, CAS latency can be set to 2 at 100 MHz or 3 at 133 MHz. This is the typical part used for most CL3 PC133 modules. A typical -7E speed rated SDRAM part can have CAS latency set to 2 at 133 MHz or 3 at 142 MHz. This is the typical part used for most CL2 PC133 modules. The serial presence detect EEPROM of my Crucial CT64M64S4WLL75.16 tells Apple Hardware Test the following:

DIMM1/J12 512 MB

PC133-322,SDRAM
CL3:7.5,CL2:10.0 Cycle (ns)
2C-0, 16LSDF6464LHG133D2
Rev.0200, 04 2D, 01

The critical portion is the following:

i CL3:7.5,CL2:10.0 Cycle (ns)

(CL3:7.5): What this means is that CL should be set to 3 for a 7.5 ns clock period (133 MHz).

(CL2:10.0): What this means is that CL can be set to 2 for a 10.0 ns clock period (100 MHz).

I'm an electrical engineer. One of the first things I ever did on the job was study an original Fujitsu SDRAM datasheet to see how it worked. Parts are rated for different CAS latency settings at different clock frequencies. The Micron SDRAM parts in my SODIMM can be safely set at CL=3 at 133 MHz or CL=2 at 100 MHz. It can be safe to use a higher CAS latency than required, but not a lower one.

Here's an example. I already said that the speed of the memory core is (relatively) independent of clock speed. Suppose it takes 15 ns from the READ command before data is ready for sampling. At 100 MHz (10 ns period) two clock periods equals 20 ns, thus allowing for CL=2. At 133 MHz (7.5 ns period) three clock periods equals 22.5 ns. You need to meet setup time requirements, so CL=3.

And if I didn't already make it clear, the job of the memory controller is to read the SPD information and see what timings are safe to run at. Although PC133 parts were specified for the OP's machine, it really runs at 100 MHz. I don't know for sure that Apple does it, but it could default to the lower CL2 for what's a CL3 part at 133 MHz.

Here's the description from P.12 of the Micron document:

CAS Latency

The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks.

Table 3: CAS Latency

SPEED / ALLOWABLE OPERATING FREQUENCY (MHZ)
SPEED / CAS LATENCY = 2 / CAS LATENCY = 3
-7E / ² 133 / ² 143
-75 / ² 100 / ² 133

What this means for a -75 part, if the clock frequency is less than 100 MHz, set CL=2. For a clock frequency higher than 100 MHz but up to 133 MHz, set CL=3. Allowable values for CAS latency are directly related to clock frequency. Most CL3 PC133 parts can be run at CL2 in PC100 applications. It's what the memory chip manufacturer recommends and all this information can be found in a module's SPD EEPROM.

As for DDR parts, this is really technical, but the following Micron document makes it clear that the same part can be rated for different CL values depending on what application (PC3200, PC2700, etc) it's used for.

http://download.micron.com/pdf/datasheets/dram/ddr/512MBDDRx4x8x16.pdf

OK, let's back up the train here. I simply made the clarification that there is no way to use CL to determine the clock speed of the RAM. For example, CL == 2 does not imply a clock speed.

I believe that you are arguing a different point.

Certainly any memory controller is built to work with memory within certain CL ratings. If the CL exceeds the specs of the memory controller, the memory will not be read correctly.

I'm an electrical engineer.

As am I.

Eneko Barrero:

i All that you say mean that in my iMac (tft 15', 800Mhz, with a 256 pc133 cl2) can I put a module of 512 so-dimm pc133 with CL3?

Sorry. I got sidetracked into an interesting technical discussion.

Yes. A PC133 SDRAM rated for either CL2 or CL3 should be able to function fine in your system. A PC133 SDRAM rated CL3 at 133 MHz most likely can be run safely at 100 MHz (your iMac's system bus speed) at CL2. I don't know if this is what your machine will do, but it is possible.

Duane:

i OK, let's back up the train here. I simply made the clarification that there is no way to use CL to determine the clock speed of the RAM. For example, CL == 2 does not imply a clock speed.

Sure. However, a "typical" PC133 SDRAM module rated at CL3 is made of -75 parts. Such parts are usually safe to set to CL2 at 100 MHz, and the SPD EEPROM will usually contain all the information needed for the system to decide whether or not it's safe to program CL to a lower (i.e. faster) setting depending on system clock frequency.

This is what you said and what I took issue with:

i Just to be clear... CL (CAS Latency) is not directly tied to PC100, PC133, or any other clock speed.

CL is programmable. If you took a look at the Micron datasheet I linked, they have a list of safe values to program CL to at *different* clock speeds. CL programming is inextricably linked to clock speed. Typically it's possible to bump down CL if you're not operating at the fastest rated clock speed of the part.

i Again CL and RAM clock speed are not directly related. You will find PC2700 (which runs at 333 MHz) and PC3200 (which runs at 400 MHz) RAM with CL's of 2 or 3.

It depends on the part. The original topic was about whether a PC133 SDRAM rated at CL3 was going to work. I simply said that it could default to the faster CL2 timing in the 100 MHz system bus of his system, and that all the information determine if this is OK is in the SPD EEPROM of the memory module.

Duane:

i OK, let's back up the train here. I simply made the clarification that there is no way to use CL to determine the clock speed of the RAM. For example, CL == 2 does not imply a clock speed.

CL=2 doesn't imply a clock speed - that's correct. However, PC133 CL2 more than likely implies a -7E (7.0 ns or 143 MHz) speed-rated SDRAM part. It would be safe to use CL=2 at 100 MHz. PC133 CL3 more than likely implies a -75 part and a safe configuration of CL=2 at 100 MHz. There is a distinct relationship between rated clock speed and safe CAS latency configuration for a given part.

i Certainly any memory controller is built to work with memory within certain CL ratings. If the CL exceeds the specs of the memory controller, the memory will not be read correctly.

There are different ways of doing that with single-data rate SDRAM. The first is simply to default to the slowest setting of CL=3. The other is to read the SPD information and determine if it's safe to use CL=2 for the given environment. I believe the latter could be done with the memory that the original poster is thinking of using. At the very least, it'll work even if it isn't extracting every last bit of performance from the SDRAM. The original poster was asking what the difference was between CL2/CL3. I was just trying to clarify that a PC133 CL3-rated RAM could be defaulting to CL2 at the 100 MHz system bus of his iMac.